![]() IEEE 1149.1-2013 PDL is used as a complement to SystemVerilog. 1149.1 PDL has specific capabilities targeted for JTAG accessible Silicon Instruments that SystemVerilog can’t achieve. Once PDL for a Silicon Instrument is validated using Synopsys VCS, the same PDL documentation can then be re-used by the SoC integrator and the ATE engineer without concern for the documentation correctness or robustness of the verification. ![]() That same instrument PDL can also be re-used by the system company using the SoC to talk to the instrument for board test or test in the field. “Synopsys has a long history of advancing product interoperability through standards bodies as well as programs of our own, such as in-Sync,” remarks Karen Bartleson, senior director of Corporate Programs and Initiatives at Synopsys, Inc.
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